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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD7665 * one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 16-bit, 570 ksps cmos adc functional block diagram dgnd dvdd avdd agnd ref refgnd switched cap dac cnvst impulse warp ognd 16 control logic and calibration circuitry clock ind(4r) 4r ovdd AD7665 ingnd pd reset byteswap ser/ par data[15:0] busy cs rd ob/ 2c serial port parallel interface ina(r) r inc(4r) 4r inb(2r) 2r features throughput: 570 ksps (warp mode) 500 ksps (normal mode) inl: 2.5 lsb max ( 0.0038% of full scale) 16-bit resolution with no missing codes s/(n+d): 90 db typ @ 180 khz thd: C100 db typ @ 180 khz analog input voltage ranges: bipolar: 10 v, 5 v, 2.5 v unipolar: 0 v to 10 v, 0 v to 5 v, 0 v to 2.5 v both ac and dc specifications no pipeline delay parallel (8/16 bits) and serial 5 v/3 v interface spi?/qspi?/microwire?/dsp compatible single 5 v supply operation power dissipation 64 mw typical 15 w @ 100 sps power-down mode: 7 w max package: 48-lead quad flatpack (lqfp) package: 48-lead chip scale (lfcsp) pin-to-pin compatible upgrade of the ad7664/ad7663 applications data acquisition communication instrumentation spectrum analysis medical instruments process control general description the AD7665 is a 16-bit, 570 ksps, charge redistribution sar, analog-to-digital converter that operates from a single 5 v power supply. it contains a high-speed 16-bit sampling adc, a resistor input scaler which allows various input ranges, an internal con- version clock, error correction circuits, and both serial and parallel system interface ports. the AD7665 is hardware factory-calibrated and is comprehen- sively tested to ensure such ac parameters as signal-to-noise ratio (snr) and total harmonic distortion (thd), in addition to the more traditional dc parameters of gain, offset, and linearity. it features a very high sampling rate mode (warp) and, for asyn- chronous conversion rate applications, a fast mode (normal) and, for low power applications, a reduced power mode (impulse) where the power is scaled with the throughput. * patent pending spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corporation it is fabricated using analog devices?high-performance, 0.6 micron cmos process and is available in a 48-lead lqfp and a tiny 48-lead lfcsp with operation specified from ?0 c to +85 c. product highlights 1. fast throughput the AD7665 is a very high-speed (570 ksps in warp mode an d 500 ksps in normal mode), charge redistribution, 16-bit sar adc. 2. single-supply operation the AD7665 operates from a single 5 v supply, dissipates only 64 mw typical, even lower when a reduced throughput is used with the reduced power mode (impulse) and a power- down mode. 3. superior inl the AD7665 has a maximum integral nonlinearity of 2.5 lsb with no missing 16-bit code. 4. serial or parallel interface versatile parallel (8 or 16 bits) or 2-wire serial interface arrangement compatible with both 3 v or 5 v logic. pulsar selection type/ksps 100-250 500-570 1000 pseudo ad7660 ad7650 differential ad7664 true bipolar ad7663 AD7665 ad7671 true differential ad7675 ad7676 ad7677
rev. a ?2? AD7665especifications parameter conditions min typ max unit resolution 16 bits analog input voltage range v ind e v ingnd 4 ref, 0 v to 4 ref, 2 ref (see table i) common-mode input voltage v ingnd e0.1 +0.5 v analog input cmrr f in = 180 khz 62 db input impedance see table i throughput speed complete cycle in warp mode 1.75 s throughput rate in warp mode 1 570 ksps time between conversions in warp mode 1 ms complete cycle in normal mode 2 s throughput rate in normal mode 0 500 ksps complete cycle in impulse mode 2.25 s throughput rate in impulse mode 0 444 ksps dc accuracy integral linearity error e2.5 +2.5 lsb 1 no missing codes 16 bits transition noise 0.7 lsb bipolar zero error 2 , t min to t max 5 v range, normal or e25 +25 lsb impulse modes other range or mode e0.06 +0.06 % of fsr bipolar full-scale error 2 , t min to t max e0.25 +0.25 % of fsr unipolar zero error 2 , t min to t max e0.18 +0.18 % of fsr unipolar full-scale error 2 , t min to t max e0.38 +0.38 % of fsr power supply sensitivity avdd = 5 v 5% 9.5 lsb ac accuracy signal-to-noise f in = 10 khz 89 90 db 3 f in = 180 khz 90 db spurious-free dynamic range f in = 180 khz 100 db total harmonic distortion f in = 180 khz e100 db signal-to-(noise+distortion) f in = 10 khz 88.5 90 db f in = 180 khz, e60 db input 30 db e3 db input bandwidth 3.6 mhz sampling dynamics aperture delay 2ns aperture jitter 5 ps rms transient response full-scale step 1 s reference external reference voltage range 2.3 2.5 avdd e 1.85 v external reference current drain 570 ksps throughput 114 a digital inputs logic levels v il e0.3 +0.8 v v ih +2.0 dvdd + 0.3 v i il e1 +1 a i ih e1 +1 a digital outputs data format parallel or serial 16-bit pipeline delay conversion results available immediately after completed conversion v ol i sink = 1.6 ma 0.4 v v oh i source = e570 a ovdd e 0.6 v power supplies specified performance avdd 4.75 5 5.25 v dvdd 4.75 5 5.25 v ovdd 2.7 5.25 4 v operating current 5 570 ksps throughput avdd 14 ma dvdd 6 4.5 ma ovdd 6 20 a (e40 c to +85 c, avdd = dvdd = 5 v, ovdd = 2.7 v to 5.25 v, unless otherwise noted.)
rev. a ?3? AD7665 parameter conditions min typ max unit power supplies (continued) power dissipation 6, 7 444 ksps throughput 8 64 74 mw 100 sps throughput 8 15 w 570 ksps throughput 5 93 107 mw in power-down mode 9 7 w temperature range 10 specified performance t min to t max e40 +85 c notes 1 lsb means least significant bit. with the 5 v input range, one lsb is 152.588 v. 2 see definition of specifications section. these specifications do not include the error contribution from the external referenc e. 3 all specifications in db are referred to a full-scale input fs. tested with an input signal at 0.5 db below full scale unless o therwise specified. 4 the max should be the minimum of 5.25 v and dvdd + 0.3 v. 5 in warp mode. 6 tested in parallel reading mode. 7 tested with the 0 v to 5 v range and v in e v ingnd = 0 v. see power dissipation section. 8 in impulse mode. 9 with ovdd below dvdd + 0.3 v and all digital inputs forced to dvdd or dgnd, respectively. 10 contact factory for extended temperature range. specifications subject to change without notice. table i. analog input configuration input voltage input range ind (4r) inc (4r) inb (2r) ina (r) impedance 1 4 ref 2 v in ingnd ingnd ref 5.85 k 2 ref v in v in ingnd ref 3.41 k ref v in v in v in ref 2.56 k 0 v to 4 ref v in v in ingnd ingnd 3.41 k 0 v to 2 ref v in v in v in ingnd 2.56 k 0 v to ref v in v in v in v in note 3 notes 1 typical analog input impedance. 2 with ref = 3 v, in this range, the input should be limited to e11 v to +12 v. 3 for this range the input is high impedance. timing specifications symbol min typ max unit refer to figures 11 and 12 convert pulsewidth t 1 5ns time between conversions t 2 1.75/2/2.25 note 1 s (warp mode/normal mode/impulse mode) cnvst s hih d s hih a s r //2 c ( /n /i a d 2 c s d c t ( /n /i //2 a t rst p r (p i cnvst data v d //2 ( /n /i data v s d 2 a r data v 2 r t ( c c avdd dvdd v vdd 2 v 2 v
rev. a AD7665 ?4? timing specifications (continued) symbol min typ max unit refer to figures 17 and 18 (ma ster serial interface modes) 2 cs snc v d cs i sc v d cs sdt d cnvst snc d (r d c 2/2/2 ( /n /i snc a sc d i sc p 2 i sc hih 2 i sc 2 sdt v s t 22 sdt v h t 2 2 sc snc d 2 cs hih snc hi 2 cs hih i sc hi 2 cs hih sdt hi 2 s hih s r a c 2 s t ii cnvst snc a d 2 //2 ( /n /i s r c snc d s d 2 r 2 (s s i sc s t sc a sdt d 2 sdin s t sdin h t sc p 2 sc hih sc nts i 2 i snc sc sdt c i s t ii r c s t ii s c t r c divsc divsc snc sc d 22 2 i sc p 2 2 i sc p 2 i sc hih 2 2 i sc 2 2 sdt v s t 22 22 22 22 sdt v h t 2 2 sc snc d 2 s hih ( 2 2 2 s hih (n 2 22 2 s hih (i 2 2 2
rev. a AD7665 ?5? pin configuration 48-lead lqfp (st-48) 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) agnd cnvst pd reset cs rd dgnd agnd avdd nc byteswap ob/ 2c warp impulse nc = no connect ser/ par d0 d1 d2/divsclk[0] busy d15 d14 d13 AD7665 d3/divsclk[1] d12 d4/ext/ int d5/invsync d6/invsclk d7/rdc/sdin ognd ovdd dvdd dgnd d8/sdout d9/sclk d10/sync d11/rderror nc nc nc nc nc ind(4r) inc(4r) inb(2r) ina(r) ingnd refgnd ref absolute maximum ratings 1 analog inputs ind 2 , inc 2 , inb 2 . . . . . . . . . . . . . . . . . . . e11 v to +30 v ina, ref, ingnd, refgnd . . . . . . . . . . . . . . . . . . . . agnd e 0.3 v to avdd + 0.3 v ground voltage differences agnd, dgnd, ognd . . . . . . . . . . . . . . . . . . . . . 0.3 v supply voltages avdd, dvdd, ovdd . . . . . . . . . . . . . . . . e0.3 v to + 7 v avdd to dvdd, avdd to ovdd . . . . . . . . . . . . . 7 v dvdd to ovdd . . . . . . . . . . . . . . . . . . . . e0.3 v to + 7 v digital inputs . . . . . . . . . . . . . . . e0.3 v to dvdd + 0.3 v internal power dissipation 3 . . . . . . . . . . . . . . . . . . . . 700 mw internal power dissipation 4 . . . . . . . . . . . . . . . . . . . . . . 2.5 w junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150 c storage temperature range . . . . . . . . . . . . e65 c to +150 c lead temperature range (soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 300 c 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 see analog input section. 3 specification is for device in free air: 48-lead lqfp: ja = 91 c/w, jc = 30 c/w. 4 specification is for device in free air: 48-lead l fcsp: jc = 26 c/w. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD7665 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ordering guide model temperature range package description package option AD7665ast e40 c to +85 c quad flatpack (lqfp) st-48 AD7665astrl e40 c to +85 c quad flatpack (lqfp) st-48 AD7665acp 1 e40 c to +85 cc hip scale (lfcsp) cp-48 AD7665acprl 1 e40 c to +85 cc hip scale (lfcsp) cp-48 eval-AD7665cb 2 evaluation board eval-control brd2 3 controller board notes 1 future product. contact factory for availability. 2 this board can be used as a standalone evaluation board or in conjunction with the eval-control brd2 for evaluation/demonstrati on purposes. 3 this board allows a pc to control and communicate with all analog devices evaluation boards ending in the cb designators. i oh 500 a 1.6ma i ol to output pin 1.4v c l 60pf * note: * in serial interface modes, the sync, sclk, and sdout timings are defined with a maximum load c l of 10pf; otherwise, the load is 60pf maximum. figure 1. load circuit for digital interface timing, sdout, sync, sclk outputs, c l = 10 pf t delay t delay 0.8v 0.8v 0.8v 2v 2v 2v figure 2. voltage reference levels for timing
rev. a AD7665 ?6? pin function description pin no. mnemonic type description 1 agnd p analog power ground pin. 2 avdd p input analog power pin. nominally 5 v. 3, 44e48 nc no connect. 4 byteswap parallel mode selection (8-/16-bit). when low, the lsb is output on d[7:0] and the msb is o utput on d[15:8]. when high, the lsb is output on d[15:8] and the msb is output on d[7:0]. 5ob/ 2c di s / t c / 2c hih s arp di s hih ips ips di s hih arp i sr/ par di s/p s i hih data data d p p d sr/ par hih 2 data2 di/ sr/ par 2 p p d divsc sr/ par hih t/ int rdc/sdin t i data di/ sr/ par p p d t/ int sr/ par hih t/ int sc t/ int hih z sc cs data di/ sr/ par p p d invsnc sr/ par hih snc snc hih hih snc data di/ sr/ par p p d i nvs c sr/ par hih sc i data di/ sr/ par p p d rdc/sdin sr/ par hih t/ int t/ int hih rdc/sdin adc sdt t sdin data sc t/ int rdc/sdin rdc/sdin hih sdt rdc/sdin sdt nd p i/ i d p vdd p i/ i d p n ( v v dvdd p d p n v 2 dnd p d p
rev. a AD7665 ?7? pin function description (continued) pin no. mnemonic type description 21 data[8] do when ser/ par p p d sdt sr/ par hih z sc c t ad s t data / 2c i t/ int sdt sc i t/ int hih i invsc sdt sc i invsc hih sdt sc 22 data di/ sr/ par p p d sc sr/ par hih t/ int t sdt invsc 2 data d sr/ par p p d snc sr /par hih z (t/ int invsnc snc hih hih sdt invsnc h snc sdt 2 data d sr/ par p p d rdrrr sr/ par hih t/ int hih i rdrrr 22 data2 d 2 p p d sr/ par hih 2 s d t hih hih t s dnd p t d rd di r d cs rd 2 cs di c s cs rd cs rst di r i hih ad c i dnd pd di pd i hih cnvst di s c a cnvst / i (ips hih arp cnvst ( / and p t a r ai r i v rnd ai r i a innd ai a i ina in ai a i r t i 2 inc ind nts ai a i di d i di/ d d d p p
rev. a AD7665 ?8? definition of specifications integral nonlinearity error (inl) linearity error refers to the deviation of each individual code f rom a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs 1/2 lsb before the first code transition. positive full scale is defined as a level 1 1/2 lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line. differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. differential nonlinearity is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. full-scale error the last transition (from 011 ...10 to 011 . . . 11 in two?s complement coding) should occur for an analog voltage 1 1/2 lsb below the nominal full scale (2.499886 v for the 2.5 v range). the full-scale error is the deviation of the actual level of the last transition from the ideal level. bipolar zero error the difference between the ideal midscale input voltage (0 v) and the actual voltage producing the midscale output code. unipolar zero error in unipolar mode, the first transition should occur at a level 1/2 lsb above analog ground. the unipolar zero error is the deviation of the actual transition from that point. spurious-free dynamic range (sfdr) the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) a measurement of the resolution with a sine wave input. it is related to s/(n+d) by the following formula: enob = ( s /[ n + d ] db e 1.76)/6.02) and is expressed in bits. total harmonic distortion (thd) t he rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. signal-to-noise ratio (snr) the ratio of the rms value of the actual input signal to the rms su m of all other spectral components below the nyquist fre- quency, excluding harmonics and dc. the value for snr is expressed in decibels. signal to (noise + distortion) ratio (s/[n+d]) the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the n yquist fre- quency, including harmonics but excluding dc. the value for s/ (n+d) is expressed in decibels. aperture delay a measure of the acquisition performance and is measured from the falling edge of the cnvst transint rspns t ad
rev. a tpc 1. integral nonlinearity vs. code tpc 2. differential nonlinearity vs. code 70 60 50 40 30 20 10 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 number of units positive inl e lsb tpc 3. typical positive inl distribution (446 units) t ypical performance characteristicseAD7665 ?9? 80 70 60 50 40 30 20 10 0 e3.0 e2.7 e2.4 e2.1 e1.8 e1.5 e1.2 e0.9 e0.6 e0.3 number of units negative inl e lsb tpc 4. typical negative inl distribution (446 units) 0019 932 7337 7204 870 22 0 0 0 1000 2000 3000 4000 5000 6000 7000 8000 7ffd 7ffe 7fff 8000 8001 8002 8003 8004 8005 8005 c ode in hexa counts tpc 5. histogram of 16,384 conversions of a dc input at the code transition 001 214 3310 9468 3259 131 100 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 7ffc 7ffd 7ffe 7fff 8000 8001 8002 8003 8004 8005 8006 c ode in hexa counts tpc 6. histogram of 16,384 conversions of a dc input at the code center
rev. a AD7665 ?10? e0 e20 e40 e60 e80 e100 e120 e140 e160 e180 0 57 114 171 228 285 amplitude e db of full scale frequency e khz 4096 point fft fs = 571khz f in = 45khz, e0.5db snr = 90.1 db sinad = 89.7db thd = e100.1db sfdr = 102.3db tpc 7. fft plot 100 95 90 85 80 75 70 1 10 100 1000 16.0 15.5 15.0 14.5 14.0 13.5 13.0 snr and s/[n +d] e db enob e bits frequency e khz snr sinad enob tpc 8. snr, s/(n+d), and enob vs. frequency 92 90 88 86 e80 e70 e60 e50 e40 e30 e20 e10 0 snr e (referred to full scale) e db input level e db tpc 9. snr vs. input level 96 93 90 87 84 e98 e100 e102 e104 e55 e35 e15 5 25 45 65 85 105 125 snr e db thd e db temperature e c thd snr tpc 10. snr, thd vs. temperature thd 2nd harmonic 3rd harmonic sfdr e60 e65 e70 e75 e80 e85 e90 e95 e100 e105 e110 e115 110 105 100 95 90 85 80 75 70 65 60 1 10 100 1000 thd, harmonics e db sfdr e db frequency e khz tpc 11. thd, harmonics, and sfdr vs. frequency e60 e70 e80 e90 e100 e110 e120 e130 e140 e150 e60 e50 e40 e30 e20 e10 0 thd, harmonics e db input level e db thd 3rd harmonic 2nd harmonic tpc 12. thd, harmonics vs. input level
rev. a AD7665 ?11? 50 40 30 20 10 0 0 50 100 150 200 t 12 delay e ns c l e pf tpc 13. typical delay vs. load capacitance c l 100000 10000 1000 100 10 1 0.1 0.01 0.001 1 10 100 1000 10000 100000 1000000 operating currents e a sampling rate e sps av dd, warp/normal dv dd, warp/normal av d d, impulse dvdd, impulse ovdd, all modes tpc 14. operating currents vs. sample rate 1000 900 800 700 600 500 400 300 200 100 0 e55 e35 e15 5 25 45 65 85 105 power-down operating currents e na temperature e c dvdd av d d ovdd tpc 15. power-down operating currents vs. temperature temperature e c 10 e10 e55 125 e35 lsb e15 5 25 4 56585105 8 0 e4 e6 e8 6 4 e2 2 offset efs +fs tpc 16. +fs, offset, and ?fs vs. temperature
rev. a AD7665 ?12? sw a comp sw b ind 4r ref refgnd lsb msb 32,768c ingnd 16,384c 4c 2c cc control logic switches control busy output code inc 4r ina r inb 2r cnvst 65,536c figure 3. adc simplified schematic circuit information the AD7665 is a fast, low-power, single-supply, precise 16-bit analog-to-digital converter (adc). the AD7665 features different modes to optimize performances according to the applications. in warp mode, the AD7665 is capable of converting 570,000 samples per second (570 ksps). the AD7665 provides the user with an on-chip track/hold, successive approximation adc that does not exhibit any pipe- line or latency, making it ideal for multiple multiplexed channel applications. it is specified to operate with both bipolar and unipolar input ranges by changing the connection of its input resistive scaler. the AD7665 can be operated from a single 5 v supply and be interfa ced to either 5 v or 3 v digital logic. it is housed in a 48-lead lqfp package or a 48-lead lfcsp package that com- bines space savings and flexible configurations as either serial or parallel interface. the AD7665 is a pin-to-pin-compatible up- grade of the ad7663 and ad7664. converter operation the AD7665 is a successive approximation analog-to-digital converter based on a charge redistribution dac. figure 3 shows the simplified schematic of the adc. the input analog signal is, first, scaled down and level-shifted by the internal input resistive scaler which allows both unipolar ranges (0 v to 2.5 v, 0 v to 5 v, and 0 to 10 v) and bipolar ranges ( 2.5 v, 5 v, and 10 v). the output voltage range of the resistive scaler is always 0 v to 2.5 v. the capacitive dac consists of an array of 16 binary weighted capacitors and an additional lsb capacitor. the comparator?s negative input is connected to a dummy capacitor of the same value as the capacitive dac array. during the acquisition phase, the common terminal of the array tied to the comparator?s positive input is connected to agnd via sw a . all independent switches are connected to the output of the resistive scaler. thus, the capacitor array is used as a sampling capacitor and acquires the analog signal. similarly, the dummy capacitor acquires the analog signal on ingnd input. when the acquisition phase is complete, and the cnvst input goes or is low, a conversion phase is initiated. when the conversion phase begins, sw a and sw b are opened first. the capacitor array and the dummy capacitor are then disconnected from the inputs and connected to the refgnd input. therefore, the differential voltage between the output of the resistive scaler and ingnd captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbal anced. by switching each element of the capacitor array between refgnd or ref, the comparator input varies by binary weighted voltage steps (v ref /2, v ref /4 ...v ref /65536). the control logic toggles these switches, starting with the msb first, in order to bring the comparator back into a balanced condition. after the completion of this process, the control logic generates the adc output code and brings busy output low. modes of operation the AD7665 features three modes of operations, warp, normal, and impulse. each of these modes is more suitable for specific applications. the warp mode allows the fastest conversion rate up to 570 ksps. however, in this mode, and this mode only, the full specified accu- racy is guaranteed only when the time between conversion does not exceed 1 ms. if the time between two consecutive conversions is longer than 1 ms, for instance, after power-up, the first con- version result should be ignored. this mode makes the AD7665 ideal for applications where both high accuracy and fast sample rate are required. the normal mode is the fastest mode (500 ksps) without any limitation about the time between conversions. this mode makes the AD7665 ideal for asynchronous applications such as data acquisition systems, where both high accuracy and fast sample rate are required. the impulse mode, the lowest power dissipation mode, allows power saving between conversions. the maximum throughput in this mode is 444 ksps. when operating at 100 sps, for example, it typically consumes only 15 w. this feature makes the AD7665 ideal for battery-powered applications. transfer functions using the ob/2c digital input, the AD7665 offers two output codings: straight binary and two?s complement. the ideal transfer characteristic for the AD7665 is shown in figure 4 and table iii. 000...000 000...001 000...010 111...101 111...110 111...111 adc code e straight binary analog input fs 1.5 lsb fs 1 lsb fs 1 lsb fs fs 0.5 lsb figure 4. adc ideal transfer function
rev. a AD7665 ?13? typical connection diagram figure 5 shows a typical connection diagram for the AD7665. different circuitry shown on this diagram is optional and is discus sed below. 100nf 10 f 100nf 10 f avdd 10 f 100nf agnd dgnd dvdd ovdd ognd ser/ par cnvst busy sdout sclk rd cs reset pd refgnd c ref 2.5v ref ref 100 d clock AD7665 c/ p/dsp serial port digital supply (3.3v or 5v) analog supply (5v) dvdd ob/ 2c note 8 byteswap dvdd 50k 100nf 1m ina 100nf u2 ind ingnd analog input ( 10v) c c 2.7nf u1 15 10 f note 2 note 1 note 3 note 7 note 4 50 inc inb note 6 notes 1. see voltage reference input chapter. 2. with the recommended voltage references, c ref is 47 f. see voltage reference input section. 3. optional circuitry for hardware gain calibration. 4. for bipolar range only. see scaler reference input section. 5. the ad8021 is recommended. see driver amplifier choice section. 6. with 0 to 2.5v range only. see analog inputs section. 7. option. see power supply section. 8. optional low jitter cnvst . see conversion control section. + + + ++ + + ad8031 ad8021 50 adr421 note 5 warp impulse figure 5. typical connection diagram ( 10 v range shown) table iii. output codes and ideal input voltages digital output code (hexa) straight two?s description analog input binary complement full-scale range 1 10 v 5 v 2.5 v 0 v to 10 v 0 v to 5 v 0 v to 2.5 v least significant bit 305.2 v 152.6 v 76.3 v 152.6 v 76.3 v 38.15 v fsr e 1 lsb 9.999695 v 4.999847 v 2.499924 v 9.999847 v 4.999924 v 2.499962 v ffff 2 7fff 2 midscale + 1 lsb 305.2 v 152.6 v 76.3 v 5.000153 v 2.570076 v 1.257038 v 8001 0001 midscale 0 v 0 v 0 v 5 v 2.5 v 1.25 v 8000 0000 midscale e 1 lsb e305.2 v e152.6 v e76.3 v 4.999847 v 2.499924 v 1.249962 v 7fff ffff efsr + 1 lsb e9.999695 v e4.999847 v e2.499924 v 152.6 v 76.3 v 38.15 v 0001 8001 efsr e10 v e5 v e2.5 v 0 v 0 v 0 v 0000 3 8000 3 notes 1 values with ref = 2.5 v, with ref = 3 v, all values will scale linearly. 2 this is also the code for an overrange analog input. 3 this is also the code for an underrange analog input.
rev. a AD7665 ?14? analog inputs the AD7665 is specified to operate with six full-scale analog input ranges. connections required for each of the four analog inputs, ind, inc, inb, ina, and the resulting full-scale ranges, are shown in table i. the typical input impedance for each analog input range is also shown. figure 6 shows a simplified analog input section of the AD7665. the four resistors connected to the four analog inputs form a resistive scaler that scales down and shifts the analog input range to a common input range of 0 v to 2.5 v at the input of the switched capacitive adc. inc inb ina 4r 2r r ind 4r agnd avdd r1 c s r = 1.28k figure 6. simplified analog input by co nnecting the four inputs ina, inb, inc, ind to the input signal itself, the ground, or a 2.5 v reference, other analog input ranges can be obtained. the diodes shown in figure 6 provide esd protection for the four analog inputs. the inputs inb, inc, ind, have a high voltage protection (e11 v to +30 v) to allow wide input voltage range. care must be taken to ensure that the analog input signal never exceeds the absolute ratings on these inputs including ina (0 v to 5 v). this will cause these diodes to become forward- biased and start conducting current. these diodes can handle a forward-biased current of 120 ma maximum. for instance, when using the 0 v to 2.5 v input range, these conditions could eventu- ally occur on the input ina when the input buffer?s (u1) supplies a re different from avdd. in such case, an input buffer with a short-circuit current limitation can be used to protect the part. 75 70 65 60 55 50 45 40 35 1 10 100 1000 10000 cmrr e db frequency e khz figure 7. analog input cmrr vs. frequency this analog input structure allows the sampling of the differential signal between the output of the resistive scaler and ingnd. unlike other converters, the ingnd input is sampled at the same time as the inputs. by using this differential input, small signals common to both inputs are rejected as shown in figure 7, which represents the typical cmrr over frequency. for instance, by using ingnd to sense a remote signal ground, the di fference of ground poten tials between the sensor and the local adc ground is eliminated. during the acquisition phase for ac signals, the AD7665 behaves like a one-pole rc filter consisting of the equivalent resistance of the resistive scaler r/2 in series with r1 and c s . the resistor r1 is typically 100 and is a lumped component made up of so me serial resistor and the on-resistance of the switches. the capacitor c s is typically 60 pf and is mainly the adc sampling capacitor. this one-pole filter with a typical e3 db cutoff frequency of 3.6 mhz reduces undesirable aliasing effects and limits the noise coming from the inputs. except when using the 0 v to 2.5 v analog input voltage range, the AD7665 has to be driven by a very low impedance source to avoid gain errors. that can be done by using a driver amplifier whose choice is eased by the primarily resistive analog input circuitry of the AD7665. when using the 0 v to 2.5 v analog input voltage range, the input impedance of the AD7665 is very high so the AD7665 can be driven directly by a low impedance source without gain error. that allows, as shown in figure 5, putting an external one-pole rc filter between the output of the amplifier output and the adc analog inputs to even further improve the noise filtering done by the AD7665 analog input circuit. however, the source impedance has to be kept low because it affects the ac performances, espe- cially the total harmonic distortion (thd). the maximum source impedance depends on the amount of total thd that can be tolerated. the thd degradation is a function of the source imped- ance and the maximum input frequency as shown in figure 8. frequency e khz e110 0 100 thd e100 e90 e80 e70 1000 r = 50 r = 11 r = 100 figure 8. thd vs. analog input frequency and input resistance (0 v to 2.5 v only)
rev. a AD7665 ?15? driver amplifier choice although the AD7665 is easy to drive, the driver amplifier needs to meet at least the following requirements: ? the driver amplifier and the AD7665 analog input circuit must be able, together, to settle for a full-scale step the capacitor array at a 16-bit level (0.0015%). in the amplifier?s data sheet, the settling at 0.1% to 0.01% is more commonly speci fied. it co uld significantly differ from the settling time at 16-bit level and it should therefore be verified prior to the driver selection. the tiny op amp ad8021, which combines ultralow noise and a high-gain bandwidth, meets this settling time requirement even when used with a high gain up to 13. ? the noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the snr and transi- tion noise performance of the AD7665. the noise coming from the driver is first scaled down by the resistive scaler according to the analog input voltage range used, and is then filtered by the AD7665 analog input circuit one-pole, low- pass filter made by (r/2 + r1) and c s . the snr degrada tion due to the amplifier is: snr f ne fsr loss db n = + 20 28 784 2 25 3 2 log . e where f e3 db is the e3 db input bandwidth in mhz of the AD7665 (3.6 mhz) or the cut-off frequ ency of the input filter if any used (0 v to 2.5 v range). n is the noise factor of the amplifier (1 if in buffer configuration). e n is the equivalent input noise voltage of the op amp in nv/(hz) 1/2 . fsr is the full-scale span (i.e., 5 v for 2.5 v range). for instance, when using the 0 v to 2.5 v range, a driver like the ad8021, with an equivalent input noise of 2 nv/
hz snr 2 t thd ad tpc thd t ad2 t ad2 t np t ad22 t ad2 ( hz i 2 t ad v r i t ad 2 v t r ad r rnd t sr r rnd t adr2 ad t adr2 t ad2 ad ad c / c s/ c n v r avdd v t snr s v r r 2 v v avdd v t (2 /2 d z t ad v s r i ( i r ad t rin ain a ad v ad t ad p s t ad v avdd v dvdd / vdd t vdd 2 v dvdd v t (dvdd rc t ad vdd dvdd v a
rev. a AD7665 ?16? 75 70 65 60 55 50 45 40 35 1 10 100 1000 psrr e db frequency e khz figure 9. psrr vs. frequency power dissipation in impulse mode, the AD7665 automatically reduces its power consumption at the end of each conversion phase. during the acquisition phase, the operating currents are very low, which allows a significant power saving when the conversion rate is reduced as shown in figure 10. this feature makes the AD7665 ideal for very low-power battery applications. 100000 10000 1000 100 10 1 0.1 1 10 100 1000 10000 100000 1000000 power dissipation e w sampling rate e sps warp/normal impulse figure 10. power dissipation vs. sample rate this does not take into account the power, if any, dissipated by the input resistive scaler which depends on the input voltage range used and the analog input voltage even in power-down mode. there is no power dissipated when the 0 v to 2.5 v is used or when both the analog input voltage is 0 v and a unipolar range, 0 to 5 v or 0 to 10 v, is used. it should be noted that the digital interface remains active even d uring the acquisition phase. to reduce the operating digital supply currents even further, the digital inputs need to be driven close to the power rails (i.e., dvdd and dgnd) and ovdd should not exceed dvdd by more than 0.3 v. conversion control figure 11 shows the detailed timing diagrams of the conversion process. the AD7665 is controlled by the signal cnvst pd t cnvst cs rd cnvst s d 2 acir cnvrt acir cnvrt c t i i c nvst s ad cnvst ad i s a cnvst i ad sps t a cnvst i cnvst ( v snr cnvst s cnvst rst data s cnvst 2 rst t
rev. a AD7665 ?17? digital interface the AD7665 has a versatile digital interface; it can be interfaced with the host system by using either a serial or parallel interface. the serial interface is multiplexed on the parallel data bus. the AD7665 digital interface also accommodates both 3 v or 5 v logic by simply connecting the ovdd supply pin of the AD7665 to the host system interface digital supply. finally, by using the ob/ 2c t cs rd cs ad ad rd cnvst s data s cs rd prvis cnvrsin data n data p d t r (c r para intrac t ad sr/ par t t crrnt cnvrsin s data s cs rd 2 s p d t r (r a c prvis cnvrsin 2 cs cnvst rd s data s s p d t r (r d c t tsap a s d s d tsap tsap s s s d s d tsap 2 d d cs t pins d hi hih t t hi hi hih t t hi 2 2 pins d rd p i sria intrac t ad sr/ par t ad s sdt t z sc t astr sria intrac i c t ad sc t/ int i snc t sc snc d rdc/sdin ad
rev. a AD7665 ?18? t 3 busy cs , rd cnvst sync sclk sdout t 28 t 29 t 14 t 18 t 19 t 20 t 21 t 24 t 26 t 27 t 23 t 22 t 16 t 15 123 141516 d15 d14 d2 d1 d0 x ext/ int = 0 rdc/sdin = 0 invsclk = invsync = 0 t 25 t 30 figure 17. master serial data timing for reading (read after convert) ext/ int = 0 rdc/sdin = 1 invsclk = invsync = 0 t 3 t 1 t 17 t 14 t 19 t 20 t 21 t 24 t 26 t 25 t 27 t 23 t 22 t 16 t 15 d15 d14 d2 d1 d0 x 12 3 141516 t 18 busy sync sclk sdout cs , rd cnvst figure 18. master serial data timing for reading (read previous conversion during convert)
rev. a AD7665 ?19? cs sclk sdout d15 d14 d1 d0 d13 x15 x14 x13 x1 x0 y15 y14 busy sdin invsclk = 0 t 35 t 36 t 37 t 31 t 32 t 16 t 33 t 34 x15 x14 x 123 1415161718 ext/ int = 1 rd = 0 figure 19. slave serial data timing for reading (read after convert) in read-during-conversion mode, the serial clock and data toggle at appropriate instants which minimizes potential feedthrough between digital activity and the critical conversion decisions. in read-after-conversion mode, it should be noted that, unlike in other modes, the signal busy returns low after the 16 data bits are pulsed out and not at the end of the conversion phase which results in a longer busy width. slave serial interface external clock the AD7665 is configured to accept an externally supplied serial data clock on the sclk pin when the ext/ int i t cs cs rd t cs t a 2 ad / t ad s s d c d r a c t a s cs rd t s a a hz ad rdc/sdin t a 2 s cnvst i rdc/sdin sc sdt h s s sc cnvst cs sc sdt rdc/sdin s s data t ad (dnstra s t cnvst cs sc ad 2 (pstra rdc/sdin sdt sc in cs in cnvst in 2 t ad dc c
rev. a AD7665 ?20? cnvst sdout sclk d1 d0 x d15 d14 d13 12 3 141516 t 3 t 35 t 36 t 37 t 31 t 32 t 16 busy invsclk = 0 cs , rd ext/ int = 1 rd = 0 figure 21. slave serial data timing for reading (read previous conversion during convert) external clock data read during conversion figure 21 shows the detailed timing diagrams of this method. during a conversion, while both cs rd t s t i rdrrr t rdc/sdin t 2 hz hz i t hz 2 hz hz icrprcssr intracin t ad t ad i/ a ad adc t ad spi adsp 2 adsp2 spi i (chc 22 ad spi chc t ad t t t (s t s p i (spi chc (str c p (cp c p (cpha spi (spi spi c r (spcr t ir (ir ptin ir chc cnvst ad s cs is/sdi sc i/ prt sdt sc invsc t/ int dvdd additina pins ittd r carit sr/ par rd 22 i ad spi i adsp2 s i a 2 ad adsp2 t (divsc t ad (t/int t a adsp2 ts adsp2 t adsp2 (irs (cr (irs as rsr (rs t adsp2 (srct adsp2 sharc adsp2
rev. a AD7665 ?21? an initial word reading has to be done after the adsp-21065l has been reset to ensure that the serial port is properly synchronized to this clock during each following data read operation. rfs adsp-21065l * sharc cnvst AD7665 * cs sync rd dr rclk flag or tfs sdout sclk invsync invsclk ext/ int rdc/sdin ser/ par dvdd * additional pins omitted for clarity figure 23. interfacing to the adsp-21065l using the serial master mode application hints layout the AD7665 has very good immunity to noise on the power supplies as can be seen in figure 9. however, care should still be taken with regard to grounding layout. the printed circuit board that houses the AD7665 should be designed so the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be easily separated. digital and analog ground planes should be joined in only one place, preferably underneath the AD7665, or, at least, as close as possible to the AD7665. if the AD7665 is in a system where multiple devices require analog-to-digital ground connections, the connection should still be made at one point only, a star ground point, which should be established as close as possible to the AD7665. it is recommended to avoid running digital lines under the device as these will couple noise onto the die. the analog ground plane should be allowed to run under the AD7665 to avoid noise coupling. fast switching signals like cnvst c t t t ad ad d avdd dvdd vdd a sr adc t dvdd ad avdd vdd dvdd avdd rc vdd dvdd t ad innd rnd and dnd nd innd rnd and adc t dnd nd t t adc z ad p a ad ad t pc c
rev. a AD7665 ?22? 48-lead quad flatpack (lqfp) (st-48) top view (pins down) 1 12 13 25 24 36 37 48 0.019 (0.5) bsc 0.276 (7.00) bsc sq 0.011 (0.27) 0.006 (0.17) 0.354 (9.00) bsc sq 0.063 (1.60) max 0.030 (0.75) 0.018 (0.45) 0.008 (0.2) 0.004 (0.09) 0 min coplanarity 0.003 (0.08) seating plane 0.006 (0.15) 0.002 (0.05) 7 0 0.057 (1.45) 0.053 (1.35) 48-lead frame chip scale package (lfcsp) (cp-48) pin 1 indicator top view 0.266 (6.75) bsc sq 0.276 (7.0) bsc sq 1 48 1 2 13 37 36 24 25 bottom view 0.215 (5.45) 0.209 (5.30) sq 0.203 (5.15) 0.024 (0.60) 0.017 (0.42) 0.009 (0.24) 0.024 (0.60) 0.017 (0.42) 0.009 (0.24) 0.020 (0.50) 0.016 (0.40) 0.012 (0.30) 0.012 (0.30) 0.009 (0.23) 0.007 (0.18) 0.020 (0.50) bsc 0.031 (0.80) max 0.026 (0.65) nom 12 max 0.039 (1.00) max 0.033 (0.85) nom 0.008 (0.20) ref 0.002 (0.05) 0.0004 (0.01) 0.0 (0.0) p addle connected to agnd controlling dimensions are in millimeters outline dimensions dimensions shown in inches and (mm).
rev. a AD7665 ?23? revision history location page data sheet changed from rev. 0 to rev. a. edits to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edit to general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 chart added to product highlights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edits to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2e3 edits to table i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 edits to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 edits to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 edits to pin function description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 addition of tpc i6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 edits to circuit information section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 edits to table iii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 new voltage reference input section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 edits to adsp-21065l in master serial interface section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 new st-48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
?24? c01846?0?5/02(a) printed in u.s.a.

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